Difference between revisions of "U23 2008/Gruppe1"

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Line 162: Line 162:
 
   
 
   
 
  }
 
  }
 +
 +
===Sourcecode: ===
 +
; Dieser Sourcecode wurde mit AVR Studio unter Windows erstellt!
 +
; Es sind kleine änderungen nötig um in mit AVRGCC zu kompilieren!
 +
 +
 +
 +
 +
 +
.include "m168def.inc"
 +
;******************************
 +
; Pin Belegung LCD
 +
;DB4-7 = PORT D. 0-3
 +
;ENABLE=PORT D Pin 7
 +
;RS= PORTD Pin 4
 +
 +
.def temp = r16
 +
.def temp1=r20
 +
.equ enable=5
 +
.equ rs=4
 +
.equ LCD_PORT = PORTD
 +
.equ LCD_DDR  = DDRD
 +
 +
.org 0x0000
 +
        rjmp    main 
 +
 +
main:
 +
 +
ldi    temp, LOW(RAMEND)    ; Stackpointer initialisieren
 +
        out    SPL, temp
 +
        ldi    temp, HIGH(RAMEND)
 +
        out    SPH, temp
 +
 +
    ldi temp,0xFF    ; Port D als Ausgang
 +
out LCD_DDR, temp
 +
 +
 +
lcdinit:  ldi temp, 0x00
 +
  out LCD_PORT, temp
 +
;******************************************
 +
; LCD mitteilen, dass im 4 Bit Modus gearbeitet wird
 +
  rcall delay15ms ;Hier mindestens 15ms warten! 
 +
  rcall delay15ms ;Zur sicherheit! z.b. nach Stromeinschalten!
 +
 +
 +
          ldi temp, 0b00000011 
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
 
 +
      rcall delay4ms        ;Mindestens 4,1ms warten!
 +
 +
  ldi temp, 0b00000011
 +
  out LCD_PORT,temp
 +
  rcall enable_routine
 +
 
 +
 +
         
 +
  rcall short_delay  ;Mindestens 100us warten!
 +
  rcall short_delay   
 +
 
 +
  ldi temp, 0b00000011
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
 
 +
 
 +
  ldi temp, 0b00000010  ;Hier wird letztendlich 4-Bit Modus eingeschaltet
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
  rcall short_delay      ;Hier zur sicherheit 60us zum abarbeiten
 +
;4 Bit Modus Mitteilung abgeschlossen
 +
; *******************************************
 +
 +
 +
  ldi temp, 0b00000010  ;2 Zeilig 5x8 matrix
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
  ldi temp,0b00001000
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
 +
      rcall short_delay  ;Kurze Wartezeit zum abarbeiten
 +
  rcall display_off
 +
  rcall clear_display
 +
 +
 +
 +
 +
 +
ldi temp, 0b00000000; Kursor nach rechts wandernd, kein display shift
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
ldi temp, 0b00000010
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
rcall delay2ms
 +
 +
rcall display_on
 +
 +
 +
   
 +
 +
 +
ldi temp, 0b00000000 ; display ein, Cursor ein, Cursor Blinkend
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
ldi temp, 0b00001111
 +
out LCD_PORT, temp
 +
rcall enable_routine ; ferig
 +
 +
ldi temp, 'H'
 +
rcall lcd_print
 +
ldi temp, 'a'
 +
rcall lcd_print
 +
 +
ldi temp, 'l'
 +
rcall lcd_print
 +
ldi temp, 'l'
 +
rcall lcd_print
 +
 +
ldi temp, 'o'
 +
rcall lcd_print
 +
ldi temp, ' '
 +
rcall lcd_print
 +
 +
ldi temp, 'W'
 +
rcall lcd_print
 +
ldi temp, 'e'
 +
rcall lcd_print
 +
 +
ldi temp, 'l'
 +
rcall lcd_print
 +
ldi temp, 't'
 +
rcall lcd_print
 +
 +
 +
         
 +
loop:
 +
  rjmp loop
 +
lcd_print: mov temp1, temp
 +
  swap temp
 +
  andi temp, 0b00001111
 +
  sbr temp, 1<<rs
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
 +
  andi temp1, 0b00001111
 +
  sbr temp1, 1<<rs
 +
  out LCD_PORT, temp1
 +
  rcall enable_routine
 +
  rcall short_delay
 +
  ret
 +
 +
display_on:
 +
ldi temp, 0b00000000
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
 +
ldi temp,0b00001100
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
rcall delay2ms
 +
 +
ret
 +
 +
display_off:
 +
ldi temp, 0b00000000
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
 +
            ldi temp, 0b00001000
 +
out LCD_PORT, temp
 +
rcall enable_routine
 +
rcall delay2ms
 +
 +
ret
 +
 +
clear_display:  
 +
  ldi temp, 0b00000000
 +
  out LCD_PORT, temp
 +
  rcall enable_routine
 +
 +
  ldi temp, 0b00000001
 +
  out LCD_PORT,temp
 +
  rcall enable_routine
 +
  rcall delay2ms
 +
 +
  ret
 +
 +
 +
enable_routine:
 +
           
 +
 +
 +
rcall short_delay
 +
sbi LCD_PORT,enable
 +
rcall short_delay
 +
cbi LCD_PORT, enable
 +
rcall short_delay
 +
 +
ret
 +
 +
delay15ms:
 +
 +
; =============================
 +
;  Warteschleifen-Generator
 +
;    340000 Zyklen:
 +
; -----------------------------
 +
; warte 339999 Zyklen:
 +
          ldi  R17, $0B
 +
WGLOOP0:  ldi  R18, $33
 +
WGLOOP1:  ldi  R19, $C9
 +
WGLOOP2:  dec  R19
 +
          brne WGLOOP2
 +
          dec  R18
 +
          brne WGLOOP1
 +
          dec  R17
 +
          brne WGLOOP0
 +
; -----------------------------
 +
; warte 1 Zyklus:
 +
          nop
 +
; =============================
 +
 +
ret
 +
 +
delay4ms:
 +
; =============================
 +
;  Warteschleifen-Generator
 +
;    90000 Zyklen: ~4,7ms
 +
; -----------------------------
 +
; warte 89997 Zyklen:
 +
          ldi  R17, $83
 +
WALOOP0:  ldi  R18, $E4
 +
WALOOP1:  dec  R18
 +
          brne WALOOP1
 +
          dec  R17
 +
          brne WALOOP0
 +
; -----------------------------
 +
; warte 3 Zyklen:
 +
          ldi  R17, $01
 +
WALOOP2:  dec  R17
 +
          brne WALOOP2
 +
; =============================
 +
ret
 +
 +
 +
delay2ms:
 +
; =============================
 +
;  Warteschleifen-Generator
 +
;    48000 Zyklen:
 +
; -----------------------------
 +
; warte 47988 Zyklen:
 +
          ldi  R17, $56
 +
WCLOOP0:  ldi  R18, $B9
 +
WCLOOP1:  dec  R18
 +
          brne WCLOOP1
 +
          dec  R17
 +
          brne WCLOOP0
 +
; -----------------------------
 +
; warte 12 Zyklen:
 +
          ldi  R17, $04
 +
WCLOOP2:  dec  R17
 +
          brne WCLOOP2
 +
; =============================
 +
 +
ret
 +
 +
short_delay:
 +
; =============================
 +
;  Warteschleifen-Generator
 +
;    1000 Zyklen: ca. 60us laut oszi
 +
;
 +
; -----------------------------
 +
; warte 999 Zyklen:
 +
          ldi  R17, $03
 +
WDLOOP0:  ldi  R18, $6E
 +
WDLOOP1:  dec  R18
 +
          brne WDLOOP1
 +
          dec  R17
 +
          brne WDLOOP0
 +
; -----------------------------
 +
; warte 1 Zyklus:
 +
          nop
 +
; =============================
 +
ret
 +
 +
 +
  
 
[[Category:U23 2008]]
 
[[Category:U23 2008]]

Revision as of 12:10, 26 August 2008

Gruppe1

Mitglieder:


-...(Hier eure Namen eintragen)
-Maike
-skullbocks
-Gesche
-Trella
-Smasher (Brille und anthrazit-farbenes dell notebook ;) )


Taster

  1. include <avr/io.h>
#include <util/delay.h>

uint8_t zeit; uint8_t richtung; uint8_t anaus;

uint8_t t0, temp0;

/*void lauflicht(void) {

}*/

void main(void) { 

 DDRC &= ~(_BV(PC0)|_BV(PC1)|_BV(PC2)|_BV(PC3)); //Schalter
 DDRC &= _BV(PC4); //Lampe4
 DDRD &= _BV(PD3) | _BV(PD6) | _BV(PD7); //Lampe 1-3
 PORTC = _BV(PC0)|_BV(PC1)|_BV(PC2)|_BV(PC3); //Pullups



 t0= 0;
 anaus = 0x00; //0x00 = aus; 0xff = an

 _delay_loop_2(0); //Kurz warten, bis pullups ready

while(1){
 	temp0 = PINC & _BV(PC0);

_delay_loop_2(0); if((PINC & _BV(PC0)) == temp0){ t0 = temp0;

}

if (t0 == 0) PORTD = 128; else PORTD = 0; 


}

}



/*if( (PINC & _BV(PC0)) == 0){ _delay_loop_2(0); if( (PINC & _BV(PC0)) == 0 ){ //anaus != anaus; PORTD = 0xff; } 

 }*/


Sourcecode, Projektabend2:

 #include <avr/io.h>
 #include <util/delay.h>
 #define GET_LAMPE(tl) ( (tl) & 0b11 )
 #define GET_ZEIT(tl) ( (tl) >> 2 )
 #define GET_TL(l,t) ( ((t)<<2) | ((l)&0b11) )
 void lampe(uint8_t l)
 { 
 	switch (l) 
 	{
 		case 0: PORTC ^= _BV(PC4);
 			break;
 		case 1: PORTD ^= _BV(PD3);
 			break;
 		case 2: PORTD ^= _BV(PD6);
 			break;
 		case 3: PORTD ^= _BV(PD7);
 			break;
 		default: break;
 	}
 }
 void zehntelsekunde(uint8_t f)
 {
 	uint8_t i;
 	for (i = 0; i < 8*f; i++) 
 		/* wait 4 * 65536 cycles */
 		_delay_loop_2(0);
 }  
 void schritt(uint8_t tl)
 {
 	lampe(GET_LAMPE(tl));
 	zehntelsekunde(GET_ZEIT(tl));
 }
 void main(void) {
 	DDRC = _BV(PC4);
 	DDRD = _BV(PD3) | _BV(PD6) | _BV(PD7); 
  	uint8_t ls[] = {GET_TL(0,10),GET_TL(2,20),GET_TL(1,50)};
 	uint8_t p=0;
  	for ( ;p <3;p++)
 		schritt(ls[p]);
  	for ( ;; ) ;
  }

Sourcecode, Projektabend1:

/*Dieses Programm lässt ein bestimmtes Muster auf unserem Testboard ablaufen*/ 

#include <avr/io.h>
#include <util/delay.h>
void lampe(uint8_t l)
{ 
	switch (l) 
	{
		case 0: PORTC ^= _BV(PC4);
			break;
		case 1: PORTD ^= _BV(PD3);
			break;
		case 2: PORTD ^= _BV(PD6);
			break;
		case 3: PORTD ^= _BV(PD7);
			break;
		default: break;
	}
}
void main(void) {
	/* config PD7 as output */

	DDRC = _BV(PC4);
	DDRD = _BV(PD3) | _BV(PD6) | _BV(PD7); 

	uint8_t ls[] = {0, 1, 0, 2, 1, 3, 2, 1, 3};
	uint8_t p=0;

	while(1) {
		//PORTD ^= _BV(PD7);
		uint8_t i;
		
		lampe(ls[p]);
		p++;
		for (i = 0; i < 76; i++) {
			/* wait 4 * 65536 cycles */
			_delay_loop_2(0);
		}
	}
	for ( ;; ) ;

}

Sourcecode:

Dieser Sourcecode wurde mit AVR Studio unter Windows erstellt!
Es sind kleine änderungen nötig um in mit AVRGCC zu kompilieren!



.include "m168def.inc"

Pin Belegung LCD
DB4-7 = PORT D. 0-3
ENABLE=PORT D Pin 7
RS= PORTD Pin 4

.def temp = r16 .def temp1=r20 .equ enable=5 .equ rs=4 .equ LCD_PORT = PORTD .equ LCD_DDR = DDRD

.org 0x0000 

       rjmp    main

main: 

		ldi     temp, LOW(RAMEND)     ; Stackpointer initialisieren
       out     SPL, temp
       ldi     temp, HIGH(RAMEND)
       out     SPH, temp

ldi temp,0xFF  ; Port D als Ausgang out LCD_DDR, temp


lcdinit: ldi temp, 0x00 out LCD_PORT, temp

LCD mitteilen, dass im 4 Bit Modus gearbeitet wird

rcall delay15ms ;Hier mindestens 15ms warten! rcall delay15ms ;Zur sicherheit! z.b. nach Stromeinschalten! 


         ldi temp, 0b00000011

out LCD_PORT, temp rcall enable_routine

rcall delay4ms  ;Mindestens 4,1ms warten!

ldi temp, 0b00000011 out LCD_PORT,temp rcall enable_routine


rcall short_delay  ;Mindestens 100us warten! rcall short_delay

ldi temp, 0b00000011 out LCD_PORT, temp rcall enable_routine


ldi temp, 0b00000010  ;Hier wird letztendlich 4-Bit Modus eingeschaltet out LCD_PORT, temp rcall enable_routine rcall short_delay  ;Hier zur sicherheit 60us zum abarbeiten

4 Bit Modus Mitteilung abgeschlossen
*******************************************


ldi temp, 0b00000010  ;2 Zeilig 5x8 matrix out LCD_PORT, temp rcall enable_routine ldi temp,0b00001000 out LCD_PORT, temp rcall enable_routine

rcall short_delay  ;Kurze Wartezeit zum abarbeiten rcall display_off rcall clear_display



ldi temp, 0b00000000; Kursor nach rechts wandernd, kein display shift out LCD_PORT, temp rcall enable_routine ldi temp, 0b00000010 out LCD_PORT, temp rcall enable_routine rcall delay2ms

rcall display_on



ldi temp, 0b00000000 ; display ein, Cursor ein, Cursor Blinkend out LCD_PORT, temp rcall enable_routine ldi temp, 0b00001111 out LCD_PORT, temp rcall enable_routine ; ferig

ldi temp, 'H' rcall lcd_print ldi temp, 'a' rcall lcd_print

ldi temp, 'l' rcall lcd_print ldi temp, 'l' rcall lcd_print

ldi temp, 'o' rcall lcd_print ldi temp, ' ' rcall lcd_print

ldi temp, 'W' rcall lcd_print ldi temp, 'e' rcall lcd_print

ldi temp, 'l' rcall lcd_print ldi temp, 't' rcall lcd_print


loop: rjmp loop lcd_print: mov temp1, temp swap temp andi temp, 0b00001111 sbr temp, 1<<rs out LCD_PORT, temp rcall enable_routine

andi temp1, 0b00001111 sbr temp1, 1<<rs out LCD_PORT, temp1 rcall enable_routine rcall short_delay ret

display_on: ldi temp, 0b00000000 out LCD_PORT, temp rcall enable_routine

ldi temp,0b00001100 out LCD_PORT, temp rcall enable_routine rcall delay2ms

ret

display_off: ldi temp, 0b00000000 out LCD_PORT, temp rcall enable_routine 

           ldi temp, 0b00001000

out LCD_PORT, temp rcall enable_routine rcall delay2ms

ret

clear_display: ldi temp, 0b00000000 out LCD_PORT, temp rcall enable_routine

ldi temp, 0b00000001 out LCD_PORT,temp rcall enable_routine rcall delay2ms

ret


enable_routine:


rcall short_delay sbi LCD_PORT,enable rcall short_delay cbi LCD_PORT, enable rcall short_delay

ret

delay15ms:

=============================
Warteschleifen-Generator
340000 Zyklen
-----------------------------
warte 339999 Zyklen
         ldi  R17, $0B

WGLOOP0: ldi R18, $33 WGLOOP1: ldi R19, $C9 WGLOOP2: dec R19 

         brne WGLOOP2
         dec  R18
         brne WGLOOP1
         dec  R17
         brne WGLOOP0
-----------------------------
warte 1 Zyklus
         nop
=============================

ret

delay4ms:

=============================
Warteschleifen-Generator
90000 Zyklen
~4,7ms
-----------------------------
warte 89997 Zyklen
         ldi  R17, $83

WALOOP0: ldi R18, $E4 WALOOP1: dec R18 

         brne WALOOP1
         dec  R17
         brne WALOOP0
-----------------------------
warte 3 Zyklen
         ldi  R17, $01

WALOOP2: dec R17 

         brne WALOOP2
=============================

ret


delay2ms:

=============================
Warteschleifen-Generator
48000 Zyklen
-----------------------------
warte 47988 Zyklen
         ldi  R17, $56

WCLOOP0: ldi R18, $B9 WCLOOP1: dec R18 

         brne WCLOOP1
         dec  R17
         brne WCLOOP0
-----------------------------
warte 12 Zyklen
         ldi  R17, $04

WCLOOP2: dec R17 

         brne WCLOOP2
=============================

ret

short_delay:

=============================
Warteschleifen-Generator
1000 Zyklen
ca. 60us laut oszi
-----------------------------
warte 999 Zyklen
         ldi  R17, $03

WDLOOP0: ldi R18, $6E WDLOOP1: dec R18 

         brne WDLOOP1
         dec  R17
         brne WDLOOP0
-----------------------------
warte 1 Zyklus
         nop
=============================

ret

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